Type
Text
Type
Dissertation
Advisor
Dorojevets, Mikhail | Doboli, Alexander | Hong, Sangjin Wong, Jennifer L.
Date
2012-05-01
Keywords
Computer engineering à Computer science à Electrical engineering | multipliers, RSFQ, superconductors | Computer engineering РComputer science РElectrical engineering
Department
Department of Computer Engineering
Language
en_US
Source
This work is sponsored by the Stony Brook University Graduate School in compliance with the requirements for completion of degree.
Identifier
http://hdl.handle.net/11401/71499
Publisher
The Graduate School, Stony Brook University: Stony Brook, NY.
Format
application/pdf
Abstract
The objective of this dissertation is to design and evaluate ultra-fast energy-efficient 32-bit integer and single-precision floating-point multipliers implemented with Rapid Single Flux Quantum (RSFQ) superconductor technology. Our goals in both multiplier designs were to design a wide datapath multipliers operating in 10 GHz+ frequencies with lowest possible latency and complexity below 100k Josephson junctions when implemented with Hypres 1.5 um 4.5 kA/cm2 fabrication process. To achieve this goal, various design techniques such as synchronous pipelining, asynchronous co-flow, and wave-pipelining are analyzed and applied throughout the design process. First, we have a brief look at CMOS computing with its power and clock frequency challenges. Then, superconductor technology is introduced, followed by a description of RSFQ logic. Next, traditional design and sequencing techniques for multiplier will be discussed. After a brief review of existing superconductor multipliers, the cell-level design of our 32-bit integer and floating-point multipliers will be presented. The microarchitectures and implementations of the 32-bit multipliers are discussed in detail along with the choice of sequencing techniques used. Our multipliers were designed and evaluated using a SBU VHDL RSFQ cell-library tuned to the Hypres 1.5 um 4.5kA/cm2 fabrication process. The simulation results for the 32-bit integer and floating-point multipliers will be presented along with statistical data about each design. Finally, we will present the design and experimental test results of an 8-bit integer RSFQ multiplier implemented with the Japanese CONNECT cell library and fabricated with ISTEC 1.0 um 10 kA/cm2 technology. | 116 pages
Recommended Citation
Kasperek, Artur Krzysztof, "32-bit Superconductor Integer and Floating-Point Multipliers" (2012). Stony Brook Theses and Dissertations Collection, 2006-2020 (closed to submissions). 705.
https://commons.library.stonybrook.edu/stony-brook-theses-and-dissertations-collection/705