Type
Text
Type
Thesis
Advisor
Hong, Sangjin. | Salman, Emre
Date
2016-12-01
Keywords
Electrical engineering | Clock Gating, Dual Edge Triggered Flip-flop, Integrated Circuit Design, Integrated Clock Gating Cell, Low Power Design, VLSI
Department
Department of Electrical Engineering.
Language
en_US
Source
This work is sponsored by the Stony Brook University Graduate School in compliance with the requirements for completion of degree.
Identifier
http://hdl.handle.net/11401/77481
Publisher
The Graduate School, Stony Brook University: Stony Brook, NY.
Format
application/pdf
Abstract
A novel glitch-free integrated clock gating (ICG) cell is developed and demonstrated in 45 nm CMOS technology. The proposed cell is more reliable as it produces an uninterrupted gated clock signal in cases where glitches occur in the enable signal during clock transitions. A detailed comparison of the proposed cell with the existing integrated clock gating cells is also presented. Glitch-free operation (and therefore high reliability) is achieved at the expense of larger power and delay, as quantified for 45 nm CMOS technology. Several design issues and different glitch characteristics are also discussed. The proposed ICG cell is shown to be highly applicable to dual edge triggered flip- flops where existing ICGs fail if there are glitches in the enable during clock transitions. | 44 pages
Recommended Citation
Noor, Tasnuva, "Design of a Novel Glitch-Free Integrated Clock Gating Cell for High Reliability" (2016). Stony Brook Theses and Dissertations Collection, 2006-2020 (closed to submissions). 3293.
https://commons.library.stonybrook.edu/stony-brook-theses-and-dissertations-collection/3293