Type
Text
Type
Thesis
Advisor
Salman, Emre | Stanacevic, Milutin
Date
2016-12-01
Keywords
Electrical engineering | Charge-recycling circuit, Phase difference deviation, Power-clock, Power consumption, Wireless energy harvesting
Department
Department of Electrical Engineering
Language
en_US
Source
This work is sponsored by the Stony Brook University Graduate School in compliance with the requirements for completion of degree.
Identifier
http://hdl.handle.net/11401/77445
Publisher
The Graduate School, Stony Brook University: Stony Brook, NY.
Format
application/pdf
Abstract
Internet-of-things (IoT) has emerged as an exciting application domain for semiconductor electronics. Recently, a new circuit design framework has been developed where charge-recycling circuits were leveraged to wirelessly power IoT based devices. Most of the existing charge-recycling circuits require multiple AC signals (referred to as power-clock signals) with certain phase difference to operate. The primary objective of this thesis is to investigate the tolerance of wirelessly powered charge-recycling circuits to non-ideal phase differences among power-clock signals. The operation principle of the most common charge-recycling (also referred to as adiabatic) circuits is described. The power consumed by efficient charge recovery logic (ECRL), complementary energy path adiabatic logic (CEPAL) and static CMOS logic are compared. The circuit considered for power comparison is a 16-bit carry select adder (CSA) and results verify that the charge-recycling operation consumes less power as compared to static CMOS logic which is in coherence with the theoretical expectation. In ECRL, each stage receives a power-clock signal that ideally should be 90$^{\circ}$ ahead of the power-clock signal of the previous stage. The VDD counterpart of static CMOS is the power-clock signal whereas the GND remains the same. In CEPAL, each logic gate employs two power-clock signals with 180$^{\circ}$ phase difference. These power-clock signals correspond to the VDD and GND in static CMOS. The 16-bit carry select adder (designed in both ECRL and CEPAL) was used to investigate the effect of non-ideal phase differences on power consumption and accuracy. The tolerance of each charge-recycling logic to phase difference deviation has been quantified. For ECRL logic, a deviation of up to 30$^{\circ}$ does not affect the power consumption and functionality, irrespective of the power-clock frequency. If the phase difference deviation is higher than 30$^{\circ}$, the power consumption significantly increases, but functionality is maintained. However for CEPAL, the tolerable deviation is inversely proportional with the power-clock frequency. For example, for a power-clock frequency of 10 MHz, CEPAL operates correctly until a phase difference deviation of 30$^{\circ}$ whereas for power-clock frequency of 30 MHz, CEPAL fails if the phase difference deviation is above 10$^{\circ}$. Furthermore, unlike ECRL, in CEPAL the non-ideal phase difference affects the functionality rather than the power consumption. | 83 pages
Recommended Citation
Panda, Sushil, "Investigating the Tolerance of Wirelessly Powered Charge-Recycling Logic to Power-Clock Phase Difference Deviations" (2016). Stony Brook Theses and Dissertations Collection, 2006-2020 (closed to submissions). 3259.
https://commons.library.stonybrook.edu/stony-brook-theses-and-dissertations-collection/3259