Type
Text
Type
Thesis
Advisor
Salman, Emre
Date
2012-05-01
Keywords
3-D IC, Decoupling capacitor, Peak noise, Power delivery, Processor-memory, TSV
Department
Department of Electrical Engineering.
Language
en_US
Source
This work is sponsored by the Stony Brook University Graduate School in compliance with the requirements for completion of degree.
Identifier
http://hdl.handle.net/11401/71075
Publisher
The Graduate School, Stony Brook University: Stony Brook, NY.
Format
application/pdf
Abstract
Three primary techniques for manufacturing through silicon vias (TSVs), viafirst, via-middle, and via-last, have been analyzed and compared to distribute power in a three-dimensional (3-D) processor-memory system with nine planes. Due to distinct fabrication techniques, these TSV technologies require significantly different design constraints, as investigated in this work. A valid design space that satisfies the peak power supply noise while minimizing area overhead is identified for each technology. It is demonstrated that the area overhead of a power distribution network with via-first TSVs is approximately 9% as compared to less than 2% in via-middle and via-last technologies. Despite this drawback, a via-first based power network is typically overdamped and the issue of resonance is alleviated. A via-last based power network, however, exhibits a relatively low damping factor and the peak noise is highly sensitive to number of TSVs and decoupling capacitance.
Recommended Citation
Satheesh, Suhas M., "Power Distribution in 3-D Processor-Memory Stacks" (2012). Stony Brook Theses and Dissertations Collection, 2006-2020 (closed to submissions). 282.
https://commons.library.stonybrook.edu/stony-brook-theses-and-dissertations-collection/282