Type
Text
Type
Thesis
Advisor
Salman, Emre. | Milder, Peter
Date
2014-12-01
Keywords
asic, checksum, fpga, hardware, implementation, parallel | Electrical engineering
Department
Department of Electrical Engineering.
Language
en_US
Source
This work is sponsored by the Stony Brook University Graduate School in compliance with the requirements for completion of degree.
Identifier
http://hdl.handle.net/11401/77480
Publisher
The Graduate School, Stony Brook University: Stony Brook, NY.
Format
application/pdf
Abstract
Checksums are utilized in many contexts such as communications, storage and reliable processing. The balance between checksum strength, implementation cost and obtained throughput often pose a challenge for present day system designers. In this research we propose two new methods for implementing the Fletcher Checksum (FC) in a parallelized context. We determined an extended parallel definition from the original FC and applied it to two different hardware implementation approaches. We then created a generator that would automatically output parameterized designs. We controlled the input word length, number of parallel inputs and architecture of the designs, and we then synthesized these designs for FPGA and ASIC. Our results show that parallelization of FC is feasible and the system throughput is proportional to the cost defined by resources used, area and power consumption. In our results, we demonstrate designs with throughput up to 375 Gbits/sec in ASIC and up to 110 Gbits/sec in FPGA, depending on the specific parameters. | 36 pages
Recommended Citation
Mera Collantes, Maria Isabel, "Parallel and Flexible Hardware Implementation of Fletcher Checksum" (2014). Stony Brook Theses and Dissertations Collection, 2006-2020 (closed to submissions). 3292.
https://commons.library.stonybrook.edu/stony-brook-theses-and-dissertations-collection/3292